Implementation of FOH for ADuC814
First order hold – definition
An "actual" FOH as a mathematical construct is a non-causal system and is not physically feasible.
There are, however, substitutes for it which are causal. Here, we used a method known as „triangle approximation“.
For more, see Franklin, G.F., J.D. Powell, and M.L. Workman, Digital Control of Dynamic Systems, Second Edition, Addison-Wesley, 1990.
The output of such causal FOH u as a function of time t is given by piecewise continuous function:
|
(1)
|
where the indices indicate the system at a discrete time, and ∆t is the sampling period.
A FOH defined in such a way brings a delay equal to one sampling period to the control loop.
The implementation of such an FOH in microprocessors, however, clashes with the fact that, in microprocessors,
time is quantised, as are the input and output signals. Hence, equation (1) must also be quantised.
Therefore the linear function is replaced with a step function. The parameters of quantisation of the time and
the output are given by the parameters of the microprocessor employed.
First order hold – implementation for ADuC814
The oscillator frequency is set to 16.777216 MHz in order to achieve maximal response rate at the DAC output for this processor.
The quantisation of the time and the output from the FOH is dependent on the absolute value of the sampling period ∆t.
The range of possible values of the absolute value of the sampling period ∆t has been divided into seven intervals, each with a defined ∆tk.
∆t / ∆tk
gives the number of segments both the time and the output gain in the sampling period will be divided into, k.
The FOH output gain is then split into that number of segments and the resulting value of the output quantity is sent in steps ∆tk to the DAC.
Any rounding is done downwards. The absolute error within the output is therefore given by
δ = ∆t – k ∆tk ,
so the maximum error tends towards ∆t_k and the maximum relative error in the output is
δmax% = (∆tk ) / (Min ∆t ) × 100.
If we label the individual steps within the sampling period by the symbol i
we can express the formula in (1) as a quantised expression:
|
(2)
|
The intervals of ∆t and the corresponding ∆tk are specified below,
along with the maximum relative error in output related to the interval:
Table 1
| Interval ∆t [s] |
∆tk [s] |
Number of
segments k |
δmax% [%] |
| Min ∆t |
Max ∆t |
| 8/128 |
64 |
1/128 |
8 – 8191 |
12.5 |
| 64 |
128 |
1/64 |
4096 – 8191 |
0.0244 |
| 128 |
256 |
1/32 |
4096 – 8191 |
0.0244 |
| 256 |
512 |
1/16 |
4096 – 8191 |
0.0244 |
| 512 |
1024 |
1/8 |
4096 – 8191 |
0.0244 |
| 1024 |
2048 |
1/4 |
4096 – 8191 |
0.0244 |
| 2048 |
4096 |
1/2 |
4096 – 8191 |
0.0244 |
Considering that the ADuC814 has a maximum output voltage of 2.5 V and 12-bit DAC,
following the procedure above we obtain the maximum possible deviation from the “true” voltage per ∆t,
∆uimax
(here, the relative error δmax% is related to the maximum output voltage):
Table 2
| Interval ∆t [s] |
∆tk [s] |
Number of
segments k |
∆uimax [V] |
δmax% [%] |
| Min ∆t |
Max ∆t |
| 8/128 |
64 |
1/128 |
8 – 8191 |
0.00061 |
0.0244 |
| 64 |
128 |
1/64 |
4096 – 8191 |
0.00061 |
0.0244 |
| 128 |
256 |
1/32 |
4096 – 8191 |
0.00061 |
0.0244 |
| 256 |
512 |
1/16 |
4096 – 8191 |
0.00061 |
0.0244 |
| 512 |
1024 |
1/8 |
4096 – 8191 |
0.00061 |
0.0244 |
| 1024 |
2048 |
1/4 |
4096 – 8191 |
0.00061 |
0.0244 |
| 2048 |
4096 |
1/2 |
4096 – 8191 |
0.00061 |
0.0244 |
For greater clarity, the situation is depicted in Figure 1 and 2:
Fig. 2 Here, the sampling period ∆t is ≈ 0.11s, which places it in the first magnitude interval.
∆tk is therefore 1/128, resulting in the division of ∆t
into 14 parts of size ∆tk
