Implementation of ZOH for ADuC814
Zero order hold – definition
The output of ZOH u as a function of time t is given by a piecewise continuous function:
|
(1)
|
The indexes indicate discrete time, ∆t is the sampling period.
Implementation of such ZOH in microprocessors is limited by the fact that in microprocessors time is quantised
and the input and output signals must also be quantised. Hence, equation (1) must also be quantised.
The parameters of quantisation of the time and the output are given by the parameter of the microprocessor employed.
Implementation of ZOH for ADuC814
The oscillator frequency is set to the default frequency of 2.097152 MHz for this microprocessor.
Quantization of time in ZOH is dependent on the size of the sampling period ∆t.
The whole domain of the allowed values ∆t is split into seven intervals, while there exists within each interval the smallest time unit ∆tk.
The magnitude of ∆tk determines the number of sections each sampling period ∆t can be split into.
The ZOH output gain is split into that number of segments and the resulting value of the output quantity is sent in steps ∆tk to the DAC.
The output of the ZOH is limited by the precision of the DAC.
The number of division steps for a given sampling period (i.e. in the given interval of values) is equal to
k = (∆t )interval / (∆tk ),
where the rounding is performed downwards in the same time. For the maximum absolute error it than limitedly stands that
δmax ≈ ∆tk ,
and for the maximum relative error of the realisation we hence get
δmax% = (∆tk ) / (Min ∆t ) × 100.
The division parameters for the individual intervals ∆t are listed in the following table:
Table 1
| Interval ∆t [s] |
∆tk [s] |
Number of
segments k |
δmax% [%] |
| Min ∆t |
Max ∆t |
| 8/128 |
64 |
1/128 |
8 – 8191 |
12.5 |
| 64 |
128 |
1/64 |
4096 – 8191 |
0.0244 |
| 128 |
256 |
1/32 |
4096 – 8191 |
0.0244 |
| 256 |
512 |
1/16 |
4096 – 8191 |
0.0244 |
| 512 |
1024 |
1/8 |
4096 – 8191 |
0.0244 |
| 1024 |
2048 |
1/4 |
4096 – 8191 |
0.0244 |
| 2048 |
4096 |
1/2 |
4096 – 8191 |
0.0244 |
Considering that the ADuC814 has a maximum output voltage of 2.5 V and 12-bit DAC, following the procedure above we obtain the maximum possible
deviation from the “true” voltage per ∆t, ∆uimax
(here, the relative error δmax% is related to the maximum output voltage):
Table 2
| Interval ∆t [s] |
∆tk [s] |
Number of
segments k |
∆uimax [V] |
δmax% [%] |
| Min ∆t |
Max ∆t |
| 8/128 |
64 |
1/128 |
8 – 8191 |
0.00061 |
0.0244 |
| 64 |
128 |
1/64 |
4096 – 8191 |
0.00061 |
0.0244 |
| 128 |
256 |
1/32 |
4096 – 8191 |
0.00061 |
0.0244 |
| 256 |
512 |
1/16 |
4096 – 8191 |
0.00061 |
0.0244 |
| 512 |
1024 |
1/8 |
4096 – 8191 |
0.00061 |
0.0244 |
| 1024 |
2048 |
1/4 |
4096 – 8191 |
0.00061 |
0.0244 |
| 2048 |
4096 |
1/2 |
4096 – 8191 |
0.00061 |
0.0244 |
For greater clarity, the situation is depicted in Figure 1:
